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71M6543F/71M6543G Data Sheet
Name
Location Rst Wk Dir
Description
00
f XTAL /2
01
f XTAL /2
10
f XTAL /2
11
f XTAL /2
FLSH_PWE
FLSH_RDE
FLSH_UNLOCK[3:0]
FLSH_WRE
IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
IE_SPI
IE_EEX
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
INTBITS
LCD_ALLCOM
LCD_BAT
LCD_BLNKMAP23[5:0]
LCD_BLNKMAP22[5:0]
LCD_CLK[1:0]
SFR B2[0]
2702[2]
2702[7:4]
2702[1]
SFR E8[0]
SFR E8[1]
SFR E8[2]
SFR E8[3]
SFR F8[7]
SFR E8[7]
SFR E8[6]
SFR E8[5]
SFR F8[6]
SFR F8[5]
2707[6:0]
2400[3]
2402[7]
2401[5:0]
2402[5:0]
2400[1:0]
0
–
0
–
0
–
0
0
0
0
0
–
0
–
0
–
–
–
–
–
R/W
R
R/W
R
R/W
R
R/W
R/W
R/W
R/W
Program Write Enable
0 = MOVX commands refer to External RAM Space, normal operation (default).
1 = MOVX @ DPTR ,A moves A to External Program Space (Flash) @ DPTR .
This bit is automatically reset after each byte written to flash. Writes to this bit are
inhibited when interrupts are enabled.
Indicates that the flash may be read by ICE or SPI slave. FLSH_RDE = (! SECURE )
Must be a 2 to enable any flash modification. See the description of Flash security for
more details.
Indicates that the flash may be written through ICE or SPI slave ports.
Interrupt flags for external interrupts 2 and 6. These flags monitor the source of the int6
and int2 interrupts (external interrupts to the MPU core). These flags are set by
hardware and must be cleared by the software interrupt handler. The IEX2 ( SFR
0xC0[1] ) and IEX6 ( SFR 0xC0[5] ) interrupt flags are automatically cleared by the MPU
core when it vectors to the interrupt handler. IEX2 and IEX6 must be cleared by writing
zero to their corresponding bit positions in SFR 0xC0, while writing ones to the other bit
positions that are not being cleared.
Interrupt inputs. The MPU may read these bits to see the input to external interrupts
INT0, INT1, up to INT6. These bits do not have any memory and are primarily intended
for debug use.
Configures SEG/COM bits as COM. Has no effect on pins whose LCD_MAP bit is zero.
Connects the LCD power supply to VBAT in all modes.
Identifies which segments connected to SEG23 and SEG22 should blink. 1 means
blink. The most significant bit corresponds to COM5, the least significant, to COM0.
Sets the LCD clock frequency. Note: f XTAL = 32768 Hz
LCD_CLK[1:0] LCD Clock Frequency
9
8
7
6
v2
107
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